Understanding Semiconductor Economics: Fabs, Fabless, and Why TSMC Holds All the Cards

Executive Summary

Semiconductors are the foundational layer of the modern economy. Every AI model, smartphone, data center, and autonomous vehicle runs on chips, and the economics of making those chips are among the most capital-intensive and strategically concentrated in any industry. The key structural fact of 2026: advanced semiconductor manufacturing — nodes below 5nm — is controlled by a single company, TSMC, which commands 90%+ of leading-edge foundry revenue. This concentration creates both extraordinary pricing power and extraordinary geopolitical risk. Understanding the fab vs. fabless split, the economics of advanced nodes, and the competitive moats involved is essential for anyone analyzing the technology supply chain.

Industry Overview

The 30-Second Version

Chip companies either make their own chips (integrated device manufacturers, or IDMs) or design chips and outsource manufacturing to foundries. NVIDIA, AMD, Apple, and Qualcomm are fabless — they design but don't manufacture. Intel is an IDM that historically designed and manufactured. TSMC is the dominant foundry. Making advanced chips requires $20–30B fabs, cutting-edge lithography machines from a single Dutch supplier (ASML), and process expertise that takes decades to develop. That stack of dependencies creates the world's most defensible industrial moat.

The Depth

The global semiconductor market is approximately $650–700B in 2026, having grown from $440B in 2020. It encompasses:

• Logic chips: CPUs, GPUs, NPUs, application processors (high value, high complexity)
• Memory: DRAM (SK Hynix, Samsung, Micron) and NAND flash (same players plus Kioxia)
• Analog & mixed-signal: Texas Instruments, Analog Devices — less talked about, extremely sticky
• Power semiconductors: ON Semi, STMicro — critical for EV and industrial applications
• Foundry services: TSMC, Samsung Foundry, GlobalFoundries, SMIC

The industry is highly cyclical at the aggregate level (inventory cycles, end-market demand swings) but structurally growing due to silicon content expansion per device and the AI-driven surge in compute demand. AI accelerators — GPUs, custom ASICs — have been the single biggest demand driver since 2023.

Node geometry is the shorthand for manufacturing complexity. A 3nm node means transistors with gate lengths in that range — though actual dimensions are now largely marketing; what matters is transistor density and power efficiency relative to prior generations. TSMC's N3 (3nm) process launched in 2022, N2 (2nm) in 2025. Each node generation requires $1–2B+ per new mask set and billions in process R&D.

How Money Flows Through the System

The Fabless Value Chain

A simplified NVIDIA GPU going from concept to data center:

1. Architecture design (NVIDIA, 1,000+ engineers, 3–4 year development cycle): Creates the chip blueprint
2. Physical design & verification (EDA tools from Synopsys, Cadence, Mentor): Translates logic to layout
3. Wafer manufacturing (TSMC): Silicon wafers processed through 1,000+ steps; NVIDIA pays $10,000–$15,000+ per wafer
4. Packaging (ASE, Amkor; advanced packaging at TSMC CoWoS): Dies stacked and interconnected
5. Test (Teradyne, Advantest): Every chip tested for function and quality
6. Board integration (ODMs, system integrators): Chip placed on PCB, integrated with memory (HBM from SK Hynix)
7. Data center sale (Microsoft, Google, Amazon, Meta buy at $30,000–$40,000 per H100/H200 unit)

NVIDIA's gross margin on H100/H200 cards runs approximately 70–75%. TSMC's wafer revenue is maybe $3,000–4,000 of the total value — foundries capture 5–15% of end product value despite being the most capital-intensive link.

TSMC's Economics

TSMC's 2025 revenue was approximately $90B, up from $75B in 2023. Gross margins run 53–56%, exceptional for manufacturing. The model: charge a premium wafer price that funds ongoing capex investment, which maintains the process lead, which justifies the premium price. A self-reinforcing loop.

Capex intensity runs 30–35% of revenue — TSMC spent roughly $30B on capex in 2025. This funds new fab construction (each leading-edge fab costs $20–25B), equipment upgrades, and R&D. The lead time from fab investment decision to production revenue is 3–5 years, making capacity planning a multi-billion-dollar bet on future demand.

Key Business Models and Their Economics

The fabless model's appeal is obvious: NVIDIA generates 73% gross margins because it monetizes IP, not silicon. AMD's transformation from near-bankruptcy in 2015 to a $200B+ company was predicated on going fabless (spinning off GlobalFoundries) and outsourcing manufacturing to TSMC, freeing capital for design investment.

Competitive Dynamics

The TSMC Moat

TSMC's competitive position is the most defensible in technology. The moat has five components:

1. Process leadership: N2 generation is 18–24 months ahead of Samsung Foundry; Intel Foundry is ~2 nodes behind on a comparable basis
2. Customer concentration and trust: Apple, NVIDIA, AMD, Qualcomm, Broadcom, and Google all rely on TSMC for leading-edge production — and critically, they are competitors of each other, making TSMC a neutral party no customer wants to defect from
3. Yield expertise: Yield (percentage of functional chips per wafer) is the most operationally sensitive variable. TSMC's yields on new nodes ramp faster than competitors. A 5-point yield advantage on a 3nm product can mean $500M in annual cost savings for a large customer
4. ASML EUV access: EUV (extreme ultraviolet) lithography is required for nodes below 7nm. ASML is the sole EUV supplier; TSMC was first to high-volume EUV production and has the most EUV tools installed globally
5. Talent density: Taiwan's semiconductor talent base — engineers trained through TSMC's programs and the broader Hsinchu ecosystem — is irreplaceable on a 10-year horizon

Intel's Foundry Bet

Intel's IDM 2.0 strategy — positioning Intel Foundry Services (IFS) as an external foundry — is the highest-stakes industrial bet in technology in 2026. Intel has secured $8.5B in CHIPS Act grants and $11B in loans from the U.S. government. However, yield challenges on Intel 18A have delayed customer tape-outs. Qualcomm and Amazon Web Services have signed as customers, but design wins at leading-edge nodes remain limited. Intel's foundry losses run $5–7B annually. The question is whether 18A can achieve the yield and performance needed to compete for AI chip production by 2027–2028.

Samsung Foundry

Samsung's 3nm GAA process launched before TSMC's N3 but suffered severe yield issues (reportedly below 35% initially vs. TSMC's 60%+). Qualcomm, which had used Samsung for some Snapdragon production, consolidated volume at TSMC. Samsung's foundry strength remains in memory integration and mature nodes, not leading-edge logic.

SMIC and China

SMIC, China's largest foundry, is constrained by U.S. export controls from accessing EUV tools. It is producing 7nm-equivalent chips using DUV multi-patterning (a workaround), but with lower yields and higher cost. SMIC's leading-edge capacity is structurally limited until China develops domestic EUV capability — a 5–10 year horizon at minimum.

The Public Market Landscape

What to Know Before You Walk Into Any Meeting on This Topic

1. The AI demand pull is structural, not cyclical: Data center capex from Microsoft, Google, Amazon, and Meta is running $200B+ annually in 2026, a large portion of which flows to semiconductor content. AI accelerator demand has de-coupled from the traditional PC/smartphone cycle.

2. Advanced packaging is the next bottleneck: CoWoS (Chip-on-Wafer-on-Substrate) at TSMC, used for HBM integration in H100/H200, was the binding constraint for NVIDIA GPU shipments in 2024. As AI chips grow denser, packaging — not just node geometry — determines performance and yield.

3. HBM is a duopoly that's printing money: High Bandwidth Memory (HBM3e) for AI accelerators is supplied primarily by SK Hynix (market leader, ~50% share) and Samsung, with Micron scaling up. HBM ASPs run 5–7x standard DRAM. SK Hynix's profit margins in 2024–2025 were transformative for the company.

4. Geopolitical risk is not hypothetical: 92% of leading-edge chip production (sub-5nm) is in Taiwan. The CHIPS Act, EU Chips Act, and Japan's Rapidus program are attempts to diversify production geography. TSMC's Arizona fabs (N4, N2 planned) are years behind Taiwan ramps and significantly higher cost. This is a long-duration risk that affects every technology investment thesis.

5. Custom Silicon is taking share from merchant chips: Apple's M-series, Google's TPUs, Amazon's Trainium/Inferentia, and Microsoft's Maia are all custom ASICs displacing NVIDIA/AMD in specific workloads. They all run on TSMC. Fabless merchant chip vendors face margin pressure from hyperscaler in-house design teams.

6. The equipment supply chain is as concentrated as the foundry market: ASML is a monopoly for EUV. Applied Materials, Lam Research, and KLA are oligopolies in deposition, etch, and inspection. These companies trade at premium multiples because every new fab — regardless of which company builds it — must buy their equipment.

Glossary of Terms That Matter

• Node / Process Node: Manufacturing generation defined by transistor dimensions; each new node improves density, power, and performance
• Fabless: Chip company that designs but does not manufacture; outsources to foundry
• IDM (Integrated Device Manufacturer): Designs and manufactures its own chips (Intel, Samsung)
• Foundry: Semiconductor manufacturer that produces chips designed by others (TSMC, Samsung Foundry)
• EUV (Extreme Ultraviolet Lithography): Manufacturing technique required for leading-edge nodes; ASML sole supplier
• HBM (High Bandwidth Memory): Stacked DRAM with high data transfer rates; critical for AI accelerators
• CoWoS: TSMC's advanced packaging technology stacking HBM alongside logic die
• Yield: Percentage of functional chips produced per wafer; higher yield = lower cost per chip
• Wafer: Silicon disc from which chips are cut; production unit for foundries
• Mask Set: Full set of photolithographic templates for a chip design; costs $5–15M for advanced nodes
• Tape-out: Final design submission to foundry before manufacturing begins
• CHIPS Act: U.S. legislation providing $52B in subsidies to onshore semiconductor manufacturing